1. Field of the Invention
The invention relates in general to an integrated circuit chip, and more particularly to a method for creating new vias (electric contacts) in the integrated circuit chip.
2. Description of the Related Art
FIG. 1 (Prior Art) is a schematic illustration showing a partial circuit layout of an integrated circuit chip 100. As shown in FIG. 1, the circuit layout of the integrated circuit chip 100 has a first metal layer M1 and a second metal layer M2 adjacent to each other. A wire 102 of the first metal layer M1 is electrically connected to a wire 104 of the second metal layer M2 through a via (electric contact). Ideally, when the integrated circuit chip 100 is being manufactured, the via can certainly electrically connect the first metal layer to the second metal layer. However, the via sometimes cannot certainly electrically connect the wire 102 to the wire 104 during the actual manufacturing process due to the following factors. For example, particles may be filled into the via or the conductive layer of the via is poorly formed. Thus, the two metal layers M1 and M2 are not certainly electrically connected to each other. Consequently, the signals in the integrated circuit chip 100 cannot be normally transmitted to the wires 102 and 104, thereby disabling the integrated circuit chip 100 from working normally.
Thus, how to provide a quick and effective method to solve the above-mentioned problems is an important subject in the IC industry.